The assignee of the present invention designs and manufactures spacecraft for communications and broadcast services. Electrical power for such spacecraft is conventionally generated by photovoltaic solar arrays, each solar array typically having several panels, each panel having many hundreds of solar cells.
A better appreciation of the presently disclosed techniques may be obtained by referring first to FIG. 1 which illustrates some typical features of solar cells and solar cell interconnects of the prior art. FIG. 1 depicts a perspective and exploded perspective view of two adjacent solar cells configured for use in a photovoltaic solar array. The solar cells 22(1) and 22(2) may each include a semiconductor substrate of silicon, gallium arsenide, germanium or other similar semiconductor materials.
A light receiving surface (referred to herein as the front facing side) of each solar cell includes a grid, typically composed of parallel spaced longitudinally extending fine metallic lines 130 that are conductively coupled to at least one current collector bar 140.
To facilitate building a solar array including a large number of individual cells, each cell may be configured as a cover integrated cell (CIC). As illustrated, for example, cell 22 includes a thin glass cover 30 adhered to the front facing side of cell 22 by an adhesive layer 31, the CIC 20 also including one or more electrically conductive interconnects 26 that may be conductively coupled to contact pads 24 that are electrically coupled with current collector bar 140.
Referring now to View B-B of FIG. 1, where rear facing side 64 of each cell includes a respective conductive surface disposed opposite to front facing side 62, it may be observed that interconnect 26 may provide an electrically conductive coupling between current collector bar 140 of a first cell 22(1) and the conductive surface of the rear facing side of an adjacent cell 22(2). It will be appreciated that a contact pad 24 may be disposed between a first end of interconnect 26 and current collector bar 140. Similarly, a contact pad 24 may be disposed between a second end of interconnect 26 and the conductive surface of the rear facing side of an adjacent cell 22(2).
Since, in typical space applications the satellites are subjected to eclipse cycles on orbit, the temperature excursion of the solar array may be in a range between −175° C. and +60° C. This temperature variation causes relative motion between cells due to the thermal expansion and contraction of the solar cells. As a result, interconnects 26 may are required to be flexible to accommodate this relative motion as indicated by the loops in the figure. It will be appreciated that a variety of arrangements of multiple solar cells (either in series or parallel connection) may be provided by appropriately coupling interconnects 26 and cells 22. The interconnect 26, or similar device, may also be used to connect other electrical components, such as a bypass diode to the cell 22.
Because the above described CIC interconnects have been produced and flown successfully in large numbers, it is highly desirable to use such interconnects for cell-to-cell electrical connection in preference to external wiring or bus bars.
Referring now to FIG. 2, it is illustrated how a bypass diode 84 may be conventionally connected in parallel with the solar cell 22 to provide current limiting protection. Bypass diode 84 may be configured to protect the solar cell 22 from damage if a solar cell is reverse biased due to a mismatch in short-circuit current capability or light shadowing between several series connected cells.
As disclosed in U.S. Pat. No. 6,034,322, assigned to the assignee of the present invention, a generally rectilinear solar cell may include one or more beveled corner edges 66, proximate to which bypass diode 84 may be advantageously disposed. More particularly, bypass diode 84 may be disposed in the phantom-lined triangular wedge-shaped volume depicted in FIG. 2. In the illustrated configuration, a first terminal of bypass diode 84 is electrically coupled to current collector bar 140 by way of upper interconnect member 92. A second terminal of bypass diode 84 is electrically coupled to a conductive surface of a rear facing side of cell 22 by way of lower interconnect member 94.
Interconnect members 92 and 94, like interconnects 26, include provisions for in plane stress relief 90 to assure integrity of assembly during repeated expansion and contraction under certain environmental conditions. Each of the upper interconnect member 92 and lower interconnect member 94 may include an interconnect made of silver or other similar metal with a stress relief feature formed between the diode and the cell, for example.
Because the above described diode interconnect members have been produced and flown successfully in large numbers, it is highly desirable to use such interconnects for diode-to-cell electrical connection as opposed to external wiring or bus bars which are more costly, less reliable, and require an appreciable amount of solar panel area that would otherwise be available for placement of solar cells.
In the configuration illustrated in FIG. 2, the bypass diode 84 is electrically connected in parallel to exactly one solar cell 22. Depending upon the reverse breakdown voltage of the cell, two or more cells connected in series may be sufficiently protected by a single bypass diode. For example, as illustrated in FIG. 3, a single bypass diode 84 may be connected in parallel to a series-connected pair of cells 22. Such a configuration, advantageously, may reduce the number of bypass diodes by a factor of two, but disadvantageously requires external wiring or bus bar 301.
As a result, improved techniques for providing bypass diode paralleled across at least two solar cells are desirable